Semiconductor wafers, such as silicon wafers, are employed as substrates in the fabrication of a wide variety of semiconductor devices and semiconductor integrated circuits. To make the wafers, bulk silicon material is first melted in a crucible at high temperature in a crystal growing furnace. An elongated cylindrical single crystal is then formed from the melt and, after cooling, sliced into thin approximately circular wafers by sawing using means well known in the art. Typical wafer dimensions are, thickness of about 0.25-1.5 mm and diameters of about 100-300 mm, although other dimensions are also used. After various lapping, etching, polishing and cleaning steps, and sometimes epitaxial layer formation, the wafers are ready for wafer processing to form the intended devices or integrated circuits. Wafer processing generally comprises a complex series of etching, oxidation, masking, doping, and deposition steps to create various N and P regions within the wafers and to create various dielectric and conductor layers on the surface of the wafers, which make up the individual devices or circuits. Many of these wafer processing steps involve exposing the wafers to high temperature, e.g., 900-1200.degree. C., for significant periods of time. Ordinarily, a wafer will contain many identical devices or circuits all fabricated at the same time.
The properties and quality of the semiconductor wafers play important roles in the difficulties encountered during wafer processing and in the final yield of working devices or circuits after wafer processing. Further, there is a complex interaction between the physical properties or state of the wafers and the various processing steps.
For example, the number of surface defects on the wafers has a great effect on wafer processing and manufacturing yield. These defects are often caused by impurities on the surface or in the bulk of the wafers and it is common to measure the surface defect density by selective etching prior to starting wafer processing. U.S. Pat. No. 4,410,395, which is incorporated herein by reference, describes a method for reducing these surface defects from 500,000 defects per square centimeter to less than 1000 defects per square centimeter. In this method, the front and back surfaces of an as-sawn wafer are lapped to remove about 35-40 micrometers of material from each side, the wafer is then heated to 1050.degree. C. for 3-4 hours or 1250.degree. C. for 1 hr. During heating most of the bulk impurities migrate to a residual strain region within 30-40 micrometers of the surface and the few that remain are trapped at deeper locations in the bulk. Following the heating step, the outer 30-40 micrometers of the surfaces of the wafer containing the trapped impurities are etched away. The etched wafer is then polished to remove an additional 20 micrometers of material from each surface. Wafers that have been lapped, heated, etched and polished as described above show much lower surface etch pit counts prior to wafer processing.
Frequently, precipitated oxygen complexes (SiO.sub.x) are introduced into the wafers in order to provide sites for immobilizing fast moving impurities. Immobilization of fast moving impurities at defect sites is referred to in the art as "gettering". Techniques for introducing and controlling the distribution of SiO.sub.x complexes or other defect centers in silicon wafers are described, for example, in U.S. Pat. Nos. 4,257,827, 4,401,506, 4,437,922, 4,597,804, 4,666,532, 4,837,172, 4,851,358, 4,661,166, 4,885,257, 4,868,133, 4,548,654, 4,314,595, and 4,659,400, which are incorporated herein by reference.
While the above-described treatments are effective in lowering the levels of defects caused by impurities associated with crystal growth and/or wafer sawing and lapping, and even may trap some residuals deep in the bulk, and further may be effective in providing surface denuded (defect-free) zones and the like, they do not prevent or avoid other problems from occurring during wafer processing. For example, the majority of heavy metal contamination present in finished wafers is usually introduced during high temperature wafer processing steps rather than during crystal growth and starting wafer preparation. This is despite the best efforts to avoid such contamination. Heavy metals are often fast diffusing species that rapidly contaminate large portions of the wafer, adversely affecting their electrical and physical properties, even when present in relatively small amounts.
One known techniques for immobilizing heavy metals is to provide bulk defects in the wafer. In lightly doped materials this is relatively easy to accomplish. However, with heavily doped N-type materials (i.e., N.sup.+) such as for example, semiconductors having resistivities of less than about 10.sup.-1 ohm-cm, prior art techniques have not been successful in providing sufficient bulk defects to getter heavy metal contamination without also introducing so much crystal damage as to render the wafers unsuitable for high yield device or circuit manufacture. There is an ongoing need to find improved means and methods for immobilizing heavy metal contamination in N.sup.+ wafers.